Identifying “Store Into Instruction Stream” (SIIS) Inefficiency by Using CPU MF Counters

This document describes a new technique to identify Store Into Instruction Stream (SIIS) inefficiency by using CPU MF Counters.

There are several components to the document. This paper describes what is SIIS, CPU MF Counters and the new metric, SIIS Indicator %, along with thresholds and recommended actions. Also provided are the slides that accompany the paper.

In addition, there is also a link to a 2006 TechDocs that describes the processor design considerations and the code it expects to execute. Finally, there is a paper that contains remediation examples of assembler programs with SIIS impacts.